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ST16-19RFRDCS
CHIP SET INTERFACE SPECIFICATION
FSD_CHIPSET_B/0104VP2
The present document contains CONFIDENTIAL INFORMATION. Please refer to last page for obligations
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. ST PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF STMicroelectronics. As used herein: 1. Life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided with the product, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
FSD_CHIPSET_B/0104VP2
CHIP SET INTERFACE SPECIFICATION
DIFFERENCES BETWEEN:
FSD_CHIPSET_B/0006VP1 AND FSD_CHIPSET_B/0104VP2
DESCRIPTION OF THE MODIFICATION Definition modification of the signal Tx-start Modification of the figure 4
PARAGRAPH ON VP2 Chapter 1.2.2 "Interface signals definition", page 2 Chapter 1.7 "FPGA pin-out & Chip Set Block Diagram", page 8
Note: other modifications which are only editorial are not described in this table.
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TABLE OF CONTENTS
1 FPGA & MCU INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 PHYSICAL INTERFACE BETWEEN FPGA AND MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1 Interface signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.2 Interface signals definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 FIFOS ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3.1 Transmission FIFO (cf figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3.2 Reception FIFO (cf figures 2 & 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3.3 Write access chronogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3.4 Read access chronogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3.5 MCU interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.1 Reception control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.2 Transmission Control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.3 Others Control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.6 REGISTERS MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6.1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6.2 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.7 FPGA PIN-OUT & CHIP SET BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 ANALOG FRONT END SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 AC/DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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FSD_CHIPSET_B/0104VP2
CHIP SET INTERFACE SPECIFICATION
LIST OF TABLES
Table 1 Table 2 Table 3 Table 4 : Interface timing ............................................................................................................. 4 : Control register description ........................................................................................... 7 : Reception status register description ............................................................................ 8 : FPGA pin out ................................................................................................................ 8
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FSD_CHIPSET_B/0104VP2
LIST OF FIGURES
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 FPGA write access chronogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 FPGA read acces chronogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 FPGA read access chronogram for last byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 The chip set diagram: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FPGA reading access chronogram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Configuration of external resonant circuit: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Preliminary Packaging Datasheet: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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CHIP SET INTERFACE SPECIFICATION
PRELIMINARY DATA
1 FPGA & MCU INTERFACE
1.1 DESCRIPTION The goal of this document is to provide a Hardware / Software interface specifications of the FPGA component (Xilinx SPARTANXL XCS40XL-4PQ208C) used in the STMicroelectronics Contactless System. The FPGA manages the communication between the MCU and the Analog Front End. This component formats the frames in accordance with ISO 14443 type B standard. 1.2 PHYSICAL INTERFACE BETWEEN FPGA AND MCU This corresponds to a classical memory interface between bidirectional Data bus, Selection signal, Read/ Write signal and a signal used to select either FIFOs or Control/Status registers access 1.2.1 Interface signals description In order to simplify interface specification, the FPGA logic has been designed with the same accesses for FIFOs and Control Registers. This is the reason why the read access chronogram show only one access type (figure 1) However, for write access chronogram, two access types are shown (figures 2 & 3). MCU accesses are done in burst mode for the FIFOs, it is not useful to generate addresses. So, there is no address bus for the MCU Interface. To address the different control registers, the two MSB bits from the data bus must be used. These control registers have to be setted during the first transmission each time the code is down loaded in FPGA (start up of the reader) or when any parameter has to be modified. For later transmissions, the control registers don't need to be re initialised. The control Register Description is available in table 2.
FSD_CHIPSET_B/0104VP2
This is a Preliminary Data on a new product now in development or undergoing evaluation. Details are subject to change without noctice.
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1.2.2 Interface signals definition The signals used for the interface between FPGA & MCU, in transmission and reception, are: Mic_Data(7:0): Data bidirectional bus. Mic_strb_b: FPGA strobe signal (Activ low) used to sample the data. This signal is sent by the MCU to the FPGA Mic_RW: Writing/Reading signal ('1'=reading, '0'=writing). This signal is sent by the MCU to the FPGA Mic_Ctrl_Data: Registers/FIFOs access signal ('1' = Register access, '0' = FIFOs access). This signal is sent by the MCU to the FPGA Tx_start: Transmission command, used to start data transmission from FIFO to output pin. This signal is sent by the MCU to the FPGA Tx_fifo_empty: Signal used to indicate transmission fifo empty. This signal is sent by the FPGA to the MCU Rx_fifo_empty: Signal used to indicate reception fifo empty. This signal is sent by the FPGA to the MCU Rx_irq_eof: IRQ reception end. This signal is sent by the FPGA to the MCU 1.3 FIFOS ACCESS 1.3.1 Transmission FIFO (cf figure 1) At the end of a transmission (or during power-on), the FPGA sets the transmission FIFO pointers to zero. This way, Tx_Fifo_Empty is validated, and so the software has to check that transmission FIFO is empty before sending a new frame. 1.3.2 Reception FIFO (cf figures 2 & 3) The reading pointer of reception FIFO is reset after each new frame received. It is impossible to get more than one frame in the FIFO. Thus, after each interruption, data stored in the FIFO has to be read until validation of Rx_Fifo_Empty signal. WARNINGS: - Reception FIFO reading is done in "lookahead" mode. Bytes are read by the FPGA in internal mode before being read by the MCU. Thus, the Rx_Fifo_Empty signal is valid just before reading the last byte in the FIFO. FIFO reception has to be read once more when Rx_Fifo_Empty is valid to get the last byte of the received frame.
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1.3.3 Write access chronogram FPGA write access chronogram, for transmission FIFO or control register: Figure 1 : FPGA write access chronogram
Mic_Ctrl_Data Mic_RW Mic_Strb_b Mic_Data(7:0) Rx_fifo_empty Rx_irq_eof Tx_start Tx_fifo_empty t1 t3 t2
t4 Data writing
Control register writing
In figure1, two types of access are shown. The first one is a Control register access (Mic_Ctrl_Data = '1') and the second one is a FIFO access (Mic_Ctrl_Data = '0'). 1.3.4 Read access chronogram FPGA read access chronogram, for reception FIFO or status register: Figure 2 FPGA read acces chronogram
Mic_Ctrl_Data Mic_RW Mic_Strb_b Mic_Data(7:0) Rx_fifo_empty Rx_irq_eof Tx_start Tx_fifo_empty t0 t1 t5 t3 t2 t6 t4 Acquisition of the next bytes, except the last one
Acquisition of the first byte
In the figure 2, prior to sending data the FPGA takes the Rx_IRQ_EOF line low to indicate to the MCU that the data can be recuperated.
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Figure 3 FPGA read access chronogram for last byte
Mic_Ctrl_Data Mic_RW Mic_Strb_b Mic_Data(7:0) Rx_fifo_empty Rx_irq_eof Tx_start Tx_fifo_empty t0 t1 t5 t3 t2 t6 t4
FSD_CHIPSET_B/0104VP2
Acquisition of the last byte
Before sending the last byte the FPGA takes the Rx_fifo_empty line high to indicate to the MCU that this is the last data. 1.3.5 MCU interface timings The following board provides interface timings (cf previous chronogram) Table 1 : Interface timing
Timing t0 t1 t2 t3 t4 t5 t6 Parameter Rx_irq_eof to Mic_Strb_b Transition Mic_Ctrl_Data, Mic_RW (and Mic_Data in writing) Setup Time before Mic_Strb_b Low Transition Mic_Ctrl_Data, Mic_RW (and Mic_Data in writing) Hold Time before Mic_Strb_b High Transition Mic_Strb_b Width Low (Activ) Mic_Strb_b Width High (Inactiv) Mic_Strb_b Activ to Valid Data in Reading Mic_Strb_b Inactiv to Tri-States Data in Reading Min. (ns) 0 0 0 240 80 240 20 Max. (ns)
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1.4 CONTROL REGISTERS 1.4.1 Reception control bits Rx_Valid_Ext: Valid_Frame signal is provided by the Analog Front End or detected by the FPGA ('1'= External Valid, '0'= Digital Detection). Rx_Speed_Auto: Reception Speed Detection ('1'= automatic, '0'= by Rx_Speed_Low Bit). Rx_Speed_Config: Reception Rate ("00"=106K, "01"=212K, "10"=424K, "11"=424K). 1.4.2 Transmission Control bits Tx_Speed_Config: Transmission Rate ("00"=106K, "01"=212K, "10"=424K, "11"=424K). Tx_Egt_Config: Number of ETU bits between data characters. Tx_CRC_Disable: Allows to insert or not the two CRC bytes at the end of the frame ('0'= CRC automatic, '1'= CRC disable). Tx_SOF_0_11: Number of '0's inside the Start Of Frame ('0'=10, '1'=11). Tx_SOF_1_3: Number of '1's inside the Start Of Frame ('0'=2, '1'=3). Tx_EOF_0_11: Number of '0's inside the End Of Frame ('0'=10, '1'=11). 1.4.3 Others Control bits Two bits control the functional mode and polarity of the interruption used to indicate the end of a received frame. Cfg_Irq_Pulse: IRQ Functionality ('0'=Toggle, '1'=Pulse). Cfg_Irq_High: Interrupt Pulse Polarity ('0'=Low, '1'=High). In order to be able to test the Card Reader functionality at power-on, it's possible to connect the transmission on the reception inside the FPGA (Loop Mode). Cfg_Loopback: Connection of the transmission on the reception. ('1'= Connection, '0'= Normal Running)
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1.5 STATUS REGISTER
FSD_CHIPSET_B/0104VP2
There is only one status register (for reception). This register can be read at the end of each reception. Its contents is modified by the end of frame interruption. It provides the status of the last received frame. In order to access this register, after the last byte received in reception, take the Mic_Ctrl_Data line high and then read the data. Rx_Speed_Value: Reception Rate ("00"=106K, "01"=212K, "10"=424K, "11"=424K). Comment: If the configuration bit Rx_Speed_Config is setting the speed, these bits are the same as configuration bits. Rx_CRC_OK: CRC Status of the frame ('1'= Wrong, '0'= OK). Rx_EGT_TooLong: Bit used to indicate EGT overrun during reception. Rx_Bad_StopBit: Bit used to indicate if a stop bit wasn't at '1' during frame reception.This is may be due to bad synchronization. If there is any mistake during the reception, this one will be stopped. In this case, the status register must be read to know the failure.
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1.6 REGISTERS MAPPING 1.6.1 Control Registers The control bits mapping is given by the following table: Table 2 : Control register description
"Address Functionality Mode Setting bit 0: bit 1: "00" bit 2: bit 3: bit 4: bit 5: Cfg_Irq_Pulse Cfg_Irq_High Cfg_Loopback ST Reserved => set to '0' ST Reserved => set to '0 ST Reserved => set to '0' '0' = Toggle Mode '0' = Pulse Activ Low '0' = Usual Functionality '1' = Pulse Mode `1' = Pulse Activ High `1' = Loop back "Description
bit [7:6]: Register Address Bits => set to "00" Reception Control bit 0: bit 1: "01" bit [3:2]: bit 4: bit 5: Rx_Valid_Ext Rx_Speed_Auto Rx_Speed_Config ST Reserved => set to '0' ST Reserved => set to '0' '0' = Digital Detection '0' = By Rx_Speed_Config Bits "00" = 106K "01" = 212K '1' = External Valid '1' = Automatic "10" & "11" = 424K
bit [7:6]: Register Address Bits => set to "01" Register 1 Transmission Control bit [1:0]: "10" bit[4:2]: bit 5: Tx_Speed_Config Tx_Egt_Config ST Reserved => set to '0' "00" = 106K "01" = 212K "10" & "11" = 424K Number of d'EGT bits
bit [7:6]: Register Address Bits => set to "10" Register 2 Transmission Control bit 0: bit 1: "11" bit 2: bit 3: bit 4: bit 5: bit [7:6]: Tx_CRC_Disable Tx_SOF_0_11 Tx_SOF_1_3 Tx_EOF_0_11 ST Reserved => set to '0' ST Reserved => set to '0' Register Address Bits => set to "11" '0' = CRC automatic '0' = SOF of 10 bits at `0' '0' = SOF of 2 bits at '1' '0' = EOF of 10 bits at '0' `1' = CRC disable '1' = SOF of 11 bits at `0' '1' = SOF of 3 bits at '1' '1' = EOF of 11 bits at '0'
Example: Register " Reception Control ": MSB 01000011 bit [7:6] "01": identification of the Register " Reception Control " bit [5:4] "00": set to '0' bit [3:2] "00": speed 106K bit 1 bit 0 '1' : automatic speed detection '1' : external valid LSB
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1.6.2 Status register The mapping of the different state bits is given by the following table: Table 3 : Reception status register description
"Address Reception Control bit [1:0]: bit 2: '0 bit 3: bit 4: bit 5: bit 6: bit 7: Rx_Speed_Value Rx_CRC_OK Rx_EGT_TooLong Rx_Bad_StopBit "00" = 106K '0' = CRC OK `0' = EGT OK "01" = 212K "Description
FSD_CHIPSET_B/0104VP2
"10" & "11"= 424K
'1' = CRC Wrong '1' = EGT too long
`0' = Stop Bit Value OK '1' = Stop Bit wrong => frame wrong?
ST Reserved => read at '0' ST Reserved => read at '0' ST Reserved => read at '0'
1.7 FPGA PIN-OUT & CHIP SET BLOCK DIAGRAM The FPGA pin-out is given by the list below: Table 4 : FPGA pin out
Signal clk1356 mic_ctrl_ndata mic_data<0> mic_data<1> mic_data<2> mic_data<3> mic_data<4> mic_data<5> mic_data<6> mic_data<7> mic_r_nw mic_strb_b reset rx_bpsk_in rx_fifo_empty rx_irq_eof rx_valid tx_fifo_empty tx_start tx_streamout Site P2 P176 P184 P185 P186 P187 P188 P189 P190 P191 P181 P179 P102 P48 P89 P180 P198 P29 P30 P37
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Figure 4 The chip set diagram:
Example: If you want to send the data '19 ', on the Tx_streamout line you will see this signal:
Tx_Streamout
Start_of_Frame Data : 19 1st Byte CRC : 38 Stop_Bit 2nd Byte CRC : 7d End_of_Frame
Start_Bit
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Example: Inputs and ouputs of the FPGA Figure 5 FPGA reading access chronogram
Mic_Ctrl_Data Mic_RW Mic_Strb_b Mic_Data(7:0) Rx_fifo_empty Rx_irq_eof Tx_start Tx_fifo_empty t0 t1 t5 t3 t2 t6 t4 Acquisition of the next bytes, except the last one
FSD_CHIPSET_B/0104VP2
Acquisition of the first byte
Example: you will find hereafter an example of the Analog front End Output. This is a BPSK signal:
Demodout (BPSK Analog Front End Output)
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2 ANALOG FRONT END SPECIFICATION
2.1 DESCRIPTION The Analog Front End is a combined RF generator and signal interface. It manages the communication between a reader so called proximity coupling device (PCDs) and a proximity contactless smartcard (PICCs). The AFE is connected to the FPGA component and the MCU used in the STMicroelectronics Contactless System (reader chip set). The Analog Front End is full ISO 14443 type B compliant. The Analog Front End operates at 13.56 MHz. As the contactless smart card carries no battery, the card is telepowered by a magnetic field, produced by the AFE, through the antenna. It also includes data modulation and demodulation circuits. The AFE is a Dil 32 with only 12 pins package. In this version, only eight pins are used, the not connected pin will be used for the extension type A (Figure 6). The device requires an external inductor, an external capacitance and resistance in order to resonate at 13.56 MHz. FC=
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Figure 7 shows a typical configuration of the external circuit for the AFE. Figure 6 Pin Configuration:
FSD_CHIPSET_B/0104VP2
Figure 7 Configuration of external resonant circuit:
2.2 FEATURES The AFE is full ISO 14443 type B compliant: - Frequency of the RF operating field is: Fo= 13,56 MHz +/- 7 kHz - Data rate from card to reader and reader to card: 106 k bits - Data modulation from reader to card:- ASK of 10%, between 6 and 14%; NRZ Data demodulation from Card to reader: BPSK NRZ load modulation, sub carrier F0/16 =847 kHz Package: DIL 32
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2.3 AC/DC ELECTRICAL CHARACTERISTICS Vcc = +12 V, Ta = 25 C, magnetic field = 7,5 A/m; unless otherwise stated.
Symbol Vcc F osc S Parameter Power supply voltage Current consumption Oscillator frequency Frequency stability Demodulator Sensibility Limits 12 140 13.56 +/-100 10 Units V mA MHz Ppm mV
2.4 ABSOLUTE MAXIMUM RATINGS
Symbol Vcc Tstg Ta parameter Maximum operating voltage Storage temperature range Operating ambient temperature range rating 18 - 20 to + 60 - 5 to + 50 units V C C
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Figure 8 Preliminary Packaging Datasheet:
FSD_CHIPSET_B/0104VP2
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3 GLOSSARY
AFE ASK BPSK CRC DIL EGT ETU FIFO FPGA IRQ ISO Standard LSB MSB MCU NRZ PCD PICC Analog Front End Amplitude Shift Keying Binary Phase Shift Keying Cyclic Redundancy Check error detection code Dual-In-Line Extra Guard Time Elementary Time Unit. Duration of one bit of data transmission First In First Out Field Programmable Gate Array Interrupt Request ISO/IEC 14443-3 Least Significant Bit Most Significant Bit Micro Controller Unit Non-Return to Zero Proximity Coupling Device Proximity Integrated Circuit Cards
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. (c) 2001 STMicroelectronics - Printed in France - All Rights Reserved BULL CP8 Patents STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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